parent
567dd3a79d
commit
5da6a6c3ee
@ -223,10 +223,10 @@ fn set_control_registers(device: &mut device::Device, index: u32, mut data: u64)
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);
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device.cpu.cop0.regs[COP0_CAUSE_REG as usize] &= !COP0_CAUSE_IP7;
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}
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COP0_STATUS_REG => {
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if data & COP0_STATUS_FR != device.cpu.cop0.regs[index as usize] & COP0_STATUS_FR {
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device::cop1::set_fgr_registers(device, data)
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}
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COP0_STATUS_REG
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if data & COP0_STATUS_FR != device.cpu.cop0.regs[index as usize] & COP0_STATUS_FR =>
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{
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device::cop1::set_fgr_registers(device, data)
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}
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_ => {}
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}
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@ -844,7 +844,7 @@ pub fn vrcpl(device: &mut device::Device, opcode: u32) {
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let vte = vte(device, vt(opcode), ve(opcode) as usize);
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let input = if device.rsp.cpu.divdp {
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((device.rsp.cpu.divin as i32) << 16)
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| get_vpr16(device.rsp.cpu.vpr[vt(opcode) as usize], ve(opcode) as u8) as u16 as i32
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| get_vpr16(device.rsp.cpu.vpr[vt(opcode) as usize], ve(opcode) as u8) as i32
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} else {
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get_vpr16(device.rsp.cpu.vpr[vt(opcode) as usize], ve(opcode) as u8) as i16 as i32
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};
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@ -901,7 +901,7 @@ pub fn vrsql(device: &mut device::Device, opcode: u32) {
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let vte = vte(device, vt(opcode), ve(opcode) as usize);
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let input = if device.rsp.cpu.divdp {
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((device.rsp.cpu.divin as i32) << 16)
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| get_vpr16(device.rsp.cpu.vpr[vt(opcode) as usize], ve(opcode) as u8) as u16 as i32
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| get_vpr16(device.rsp.cpu.vpr[vt(opcode) as usize], ve(opcode) as u8) as i32
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} else {
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get_vpr16(device.rsp.cpu.vpr[vt(opcode) as usize], ve(opcode) as u8) as i16 as i32
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};
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