From ad8e64ede57799884de11a06a0e2b9e8ba6e4271 Mon Sep 17 00:00:00 2001
From: Logan McNaughton <848146+loganmc10@users.noreply.github.com>
Date: Thu, 5 Oct 2023 12:20:37 -0600
Subject: [PATCH] add cycles

---
 src/device/sram.rs | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/device/sram.rs b/src/device/sram.rs
index c95f0ca..355ebdc 100644
--- a/src/device/sram.rs
+++ b/src/device/sram.rs
@@ -8,6 +8,9 @@ pub fn read_mem(
     address: u64,
     _access_size: device::memory::AccessSize,
 ) -> u32 {
+    let cycles = device::pi::calculate_cycles(device, 2, 4);
+    device::cop0::add_cycles(device, cycles);
+
     if device.ui.save_type.contains(&ui::storage::SaveTypes::Sram) {
         let masked_address = address as usize & SRAM_MASK;
 
@@ -46,6 +49,16 @@ pub fn write_mem(device: &mut device::Device, address: u64, value: u32, mask: u3
     } else {
         panic!("flash write")
     }
+
+    device.pi.regs[device::pi::PI_STATUS_REG as usize] |= device::pi::PI_STATUS_IO_BUSY;
+
+    let cycles = device::pi::calculate_cycles(device, 2, 4);
+    device::events::create_event(
+        device,
+        device::events::EventType::PI,
+        device.cpu.cop0.regs[device::cop0::COP0_COUNT_REG as usize] + cycles,
+        device::pi::dma_event,
+    );
 }
 
 // cart is big endian, rdram is native endian