166 lines
5.8 KiB
Rust
166 lines
5.8 KiB
Rust
use crate::device;
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use crate::ui;
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pub const DPC_START_REG: u32 = 0;
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pub const DPC_END_REG: u32 = 1;
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pub const DPC_CURRENT_REG: u32 = 2;
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pub const DPC_STATUS_REG: u32 = 3;
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pub const DPC_CLOCK_REG: u32 = 4;
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pub const DPC_BUFBUSY_REG: u32 = 5;
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pub const DPC_PIPEBUSY_REG: u32 = 6;
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pub const DPC_TMEM_REG: u32 = 7;
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pub const DPC_REGS_COUNT: u32 = 8;
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//pub const DPS_TBIST_REG: u32 = 0;
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//pub const DPS_TEST_MODE_REG: u32 = 1;
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//pub const DPS_BUFTEST_ADDR_REG: u32 = 2;
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//pub const DPS_BUFTEST_DATA_REG: u32 = 3;
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pub const DPS_REGS_COUNT: u32 = 4;
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/* DPC status - read */
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pub const DPC_STATUS_XBUS_DMEM_DMA: u32 = 1 << 0;
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pub const DPC_STATUS_FREEZE: u32 = 1 << 1;
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pub const DPC_STATUS_FLUSH: u32 = 1 << 2;
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pub const DPC_STATUS_START_GCLK: u32 = 1 << 3;
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pub const DPC_STATUS_TMEM_BUSY: u32 = 1 << 4;
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pub const DPC_STATUS_PIPE_BUSY: u32 = 1 << 5;
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pub const DPC_STATUS_CMD_BUSY: u32 = 1 << 6;
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pub const DPC_STATUS_CBUF_READY: u32 = 1 << 7;
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//pub const DPC_STATUS_DMA_BUSY: u32 = 1 << 8;
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//pub const DPC_STATUS_END_VALID: u32 = 1 << 9;
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pub const DPC_STATUS_START_VALID: u32 = 1 << 10;
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/* DPC status - write */
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pub const DPC_CLR_XBUS_DMEM_DMA: u32 = 1 << 0;
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pub const DPC_SET_XBUS_DMEM_DMA: u32 = 1 << 1;
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pub const DPC_CLR_FREEZE: u32 = 1 << 2;
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pub const DPC_SET_FREEZE: u32 = 1 << 3;
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pub const DPC_CLR_FLUSH: u32 = 1 << 4;
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pub const DPC_SET_FLUSH: u32 = 1 << 5;
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pub const DPC_CLR_TMEM_CTR: u32 = 1 << 6;
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pub const DPC_CLR_PIPE_CTR: u32 = 1 << 7;
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pub const DPC_CLR_CMD_CTR: u32 = 1 << 8;
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pub const DPC_CLR_CLOCK_CTR: u32 = 1 << 9;
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pub struct Rdp {
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pub regs_dpc: [u32; DPC_REGS_COUNT as usize],
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pub regs_dps: [u32; DPS_REGS_COUNT as usize],
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}
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pub fn read_regs_dpc(
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device: &mut device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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return device.rdp.regs_dpc[((address & 0xFFFF) >> 2) as usize];
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}
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pub fn write_regs_dpc(device: &mut device::Device, address: u64, value: u32, mask: u32) {
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let reg = (address & 0xFFFF) >> 2;
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match reg as u32 {
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DPC_CURRENT_REG | DPC_CLOCK_REG | DPC_BUFBUSY_REG | DPC_PIPEBUSY_REG | DPC_TMEM_REG => {}
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DPC_STATUS_REG => update_dpc_status(device, value & mask),
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DPC_START_REG => {
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if (device.rdp.regs_dpc[DPC_STATUS_REG as usize] & DPC_STATUS_START_VALID) == 0 {
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device::memory::masked_write_32(
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&mut device.rdp.regs_dpc[reg as usize],
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value & 0xFFFFF8,
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mask,
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)
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}
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] |= DPC_STATUS_START_VALID
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}
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DPC_END_REG => {
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device::memory::masked_write_32(
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&mut device.rdp.regs_dpc[reg as usize],
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value & 0xFFFFF8,
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mask,
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);
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if (device.rdp.regs_dpc[DPC_STATUS_REG as usize] & DPC_STATUS_START_VALID) != 0 {
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device.rdp.regs_dpc[DPC_CURRENT_REG as usize] =
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device.rdp.regs_dpc[DPC_START_REG as usize];
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] &= !DPC_STATUS_START_VALID
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}
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let timer = ui::video::process_rdp_list(&mut device.rdp.regs_dpc, &mut device.rsp.mem);
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if timer != 0 {
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device::events::create_event(
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device,
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device::events::EventType::DP,
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device.cpu.cop0.regs[device::cop0::COP0_COUNT_REG as usize] + timer,
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rdp_interrupt_event,
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)
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}
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}
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_ => device::memory::masked_write_32(&mut device.rdp.regs_dpc[reg as usize], value, mask),
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}
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}
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pub fn read_regs_dps(
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device: &mut device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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return device.rdp.regs_dps[((address & 0xFFFF) >> 2) as usize];
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}
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pub fn write_regs_dps(device: &mut device::Device, address: u64, value: u32, mask: u32) {
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device::memory::masked_write_32(
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&mut device.rdp.regs_dps[((address & 0xFFFF) >> 2) as usize],
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value,
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mask,
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)
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}
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pub fn update_dpc_status(device: &mut device::Device, w: u32) {
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/* clear / set xbus_dmem_dma */
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if w & DPC_CLR_XBUS_DMEM_DMA != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] &= !DPC_STATUS_XBUS_DMEM_DMA
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}
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if w & DPC_SET_XBUS_DMEM_DMA != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] |= DPC_STATUS_XBUS_DMEM_DMA
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}
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/* clear / set freeze */
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if w & DPC_CLR_FREEZE != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] &= !DPC_STATUS_FREEZE
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}
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if w & DPC_SET_FREEZE != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] |= DPC_STATUS_FREEZE
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}
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/* clear / set flush */
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if w & DPC_CLR_FLUSH != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] &= !DPC_STATUS_FLUSH
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}
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if w & DPC_SET_FLUSH != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] |= DPC_STATUS_FLUSH
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}
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if w & DPC_CLR_TMEM_CTR != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] &= !DPC_STATUS_TMEM_BUSY;
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device.rdp.regs_dpc[DPC_TMEM_REG as usize] = 0
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}
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if w & DPC_CLR_PIPE_CTR != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] &= !DPC_STATUS_PIPE_BUSY;
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device.rdp.regs_dpc[DPC_PIPEBUSY_REG as usize] = 0
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}
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if w & DPC_CLR_CMD_CTR != 0 {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] &= !DPC_STATUS_CMD_BUSY;
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device.rdp.regs_dpc[DPC_BUFBUSY_REG as usize] = 0
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}
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/* clear clock counter */
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if w & DPC_CLR_CLOCK_CTR != 0 {
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device.rdp.regs_dpc[DPC_CLOCK_REG as usize] = 0
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}
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}
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pub fn init(device: &mut device::Device) {
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device.rdp.regs_dpc[DPC_STATUS_REG as usize] |=
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DPC_STATUS_START_GCLK | DPC_STATUS_PIPE_BUSY | DPC_STATUS_CBUF_READY;
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}
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pub fn rdp_interrupt_event(device: &mut device::Device) {
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ui::video::rdp_full_sync();
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device::mi::set_rcp_interrupt(device, device::mi::MI_INTR_DP)
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}
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