120 lines
3.7 KiB
Rust
120 lines
3.7 KiB
Rust
use crate::device;
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pub const SI_DRAM_ADDR_REG: u32 = 0;
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pub const SI_PIF_ADDR_RD64B_REG: u32 = 1;
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//pub const SI_R2_REG: u32 = 2;
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//pub const SI_R3_REG: u32 = 3;
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pub const SI_PIF_ADDR_WR64B_REG: u32 = 4;
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//pub const SI_R5_REG: u32 = 5;
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pub const SI_STATUS_REG: u32 = 6;
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pub const SI_REGS_COUNT: u32 = 7;
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pub const SI_STATUS_DMA_BUSY: u32 = 1 << 0;
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pub const SI_STATUS_IO_BUSY: u32 = 1 << 1;
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//pub const SI_STATUS_DMA_ERROR: u32 = 1 << 3;
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pub const SI_STATUS_INTERRUPT: u32 = 1 << 12;
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#[derive(PartialEq)]
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pub enum DmaDir {
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None,
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Write,
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Read,
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}
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pub struct Si {
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pub regs: [u32; SI_REGS_COUNT as usize],
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pub dma_dir: DmaDir,
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}
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pub fn read_regs(
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device: &mut device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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return device.si.regs[((address & 0xFFFF) >> 2) as usize];
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}
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pub fn dma_read(device: &mut device::Device) {
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device.si.dma_dir = DmaDir::Read;
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let duration = device::pif::update_pif_ram(device);
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device.si.regs[SI_STATUS_REG as usize] |= SI_STATUS_DMA_BUSY;
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device::events::create_event(
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device,
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device::events::EventType::SI,
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device.cpu.cop0.regs[device::cop0::COP0_COUNT_REG as usize] + duration,
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dma_event,
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)
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}
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pub fn dma_write(device: &mut device::Device) {
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device.si.dma_dir = DmaDir::Write;
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copy_pif_rdram(device);
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device.si.regs[SI_STATUS_REG as usize] |= SI_STATUS_DMA_BUSY;
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device::events::create_event(
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device,
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device::events::EventType::SI,
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device.cpu.cop0.regs[device::cop0::COP0_COUNT_REG as usize] + 5200, //based on https://github.com/rasky/n64-systembench
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dma_event,
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)
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}
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pub fn write_regs(device: &mut device::Device, address: u64, value: u32, mask: u32) {
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let reg = (address & 0xFFFF) >> 2;
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match reg as u32 {
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SI_STATUS_REG => {
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device.si.regs[reg as usize] &= !SI_STATUS_INTERRUPT;
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device::mi::clear_rcp_interrupt(device, device::mi::MI_INTR_SI)
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}
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SI_PIF_ADDR_RD64B_REG => dma_read(device),
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SI_PIF_ADDR_WR64B_REG => dma_write(device),
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_ => device::memory::masked_write_32(&mut device.si.regs[reg as usize], value, mask),
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}
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}
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//rdram is in native endian format, and pif memory is in big endian format
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pub fn copy_pif_rdram(device: &mut device::Device) {
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let dram_addr = device.si.regs[SI_DRAM_ADDR_REG as usize] as usize & device::rdram::RDRAM_MASK;
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if device.si.dma_dir == DmaDir::Write {
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let mut i = 0;
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while i < device::pif::PIF_RAM_SIZE {
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let data = u32::from_ne_bytes(
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device.rdram.mem[dram_addr + i..dram_addr + i + 4]
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.try_into()
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.unwrap(),
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);
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device.pif.ram[i..i + 4].copy_from_slice(&data.to_be_bytes());
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i += 4;
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}
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} else if device.si.dma_dir == DmaDir::Read {
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let mut i = 0;
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while i < device::pif::PIF_RAM_SIZE {
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let data = u32::from_be_bytes(device.pif.ram[i..i + 4].try_into().unwrap());
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device.rdram.mem[dram_addr + i..dram_addr + i + 4].copy_from_slice(&data.to_ne_bytes());
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i += 4;
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}
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} else {
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panic!("si dma unknown")
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}
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}
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pub fn dma_event(device: &mut device::Device) {
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if device.si.dma_dir == DmaDir::Write {
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device::pif::process_ram(device);
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} else if device.si.dma_dir == DmaDir::Read {
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device::si::copy_pif_rdram(device);
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} else {
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panic!("si dma unknown")
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}
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device.si.dma_dir = DmaDir::None;
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device.si.regs[SI_STATUS_REG as usize] &= !(SI_STATUS_DMA_BUSY | SI_STATUS_IO_BUSY);
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device.si.regs[SI_STATUS_REG as usize] |= SI_STATUS_INTERRUPT;
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device::mi::set_rcp_interrupt(device, device::mi::MI_INTR_SI)
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}
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