Remove pub modifier for consts (#114)

2025-01-07 19:54:15 +01:00 · 2025-01-07 19:54:15 +01:00 · e02add9676
commit e02add9676
parent 24b464fea4
18 changed files with 272 additions and 272 deletions
--- a/src/device/ai.rs
+++ b/src/device/ai.rs
@ -1,16 +1,16 @@
 use crate::device;
 use crate::ui;

-pub const AI_DRAM_ADDR_REG: u32 = 0;
-pub const AI_LEN_REG: u32 = 1;
-//pub const AI_CONTROL_REG: u32 = 2;
-pub const AI_STATUS_REG: u32 = 3;
-pub const AI_DACRATE_REG: u32 = 4;
-//pub const AI_BITRATE_REG: u32 = 5;
+const AI_DRAM_ADDR_REG: u32 = 0;
+const AI_LEN_REG: u32 = 1;
+// const AI_CONTROL_REG: u32 = 2;
+const AI_STATUS_REG: u32 = 3;
+const AI_DACRATE_REG: u32 = 4;
+// const AI_BITRATE_REG: u32 = 5;
 pub const AI_REGS_COUNT: u32 = 6;

-pub const AI_STATUS_BUSY: u32 = 0x40000000;
-pub const AI_STATUS_FULL: u32 = 0x80000000;
+const AI_STATUS_BUSY: u32 = 0x40000000;
+const AI_STATUS_FULL: u32 = 0x80000000;

 pub struct Ai {
    pub regs: [u32; AI_REGS_COUNT as usize],
--- a/src/device/cart.rs
+++ b/src/device/cart.rs
@ -4,19 +4,19 @@ use chrono::Timelike;
 use crate::device;
 use crate::ui;

-pub const JCMD_STATUS: u8 = 0x00;
-pub const JCMD_EEPROM_READ: u8 = 0x04;
-pub const JCMD_EEPROM_WRITE: u8 = 0x05;
-pub const JCMD_AF_RTC_STATUS: u8 = 0x06;
-pub const JCMD_AF_RTC_READ: u8 = 0x07;
-pub const JCMD_AF_RTC_WRITE: u8 = 0x08;
-pub const JCMD_RESET: u8 = 0xff;
+const JCMD_STATUS: u8 = 0x00;
+const JCMD_EEPROM_READ: u8 = 0x04;
+const JCMD_EEPROM_WRITE: u8 = 0x05;
+const JCMD_AF_RTC_STATUS: u8 = 0x06;
+const JCMD_AF_RTC_READ: u8 = 0x07;
+const JCMD_AF_RTC_WRITE: u8 = 0x08;
+const JCMD_RESET: u8 = 0xff;

-pub const JDT_AF_RTC: u16 = 0x1000; /* RTC */
-pub const JDT_EEPROM_4K: u16 = 0x8000; /* 4k EEPROM */
-pub const JDT_EEPROM_16K: u16 = 0xc000; /* 16k EEPROM */
-pub const EEPROM_BLOCK_SIZE: usize = 8;
-pub const EEPROM_MAX_SIZE: usize = 0x800;
+const JDT_AF_RTC: u16 = 0x1000; /* RTC */
+const JDT_EEPROM_4K: u16 = 0x8000; /* 4k EEPROM */
+const JDT_EEPROM_16K: u16 = 0xc000; /* 16k EEPROM */
+const EEPROM_BLOCK_SIZE: usize = 8;
+const EEPROM_MAX_SIZE: usize = 0x800;

 pub struct AfRtc {
    pub control: u16,
--- a/src/device/cart_rom.rs
+++ b/src/device/cart_rom.rs
@ -10,7 +10,7 @@ pub enum CicType {
    CicNus5167,
 }

-pub const CART_MASK: usize = 0xFFFFFFF;
+const CART_MASK: usize = 0xFFFFFFF;
 pub struct Cart {
    pub rom: Vec<u8>,
    pub is_viewer_buffer: [u8; 0xFFFF],
--- a/src/device/controller.rs
+++ b/src/device/controller.rs
@ -1,26 +1,26 @@
 use crate::device;
 use crate::ui;

-pub const JCMD_STATUS: u8 = 0x00;
-pub const JCMD_CONTROLLER_READ: u8 = 0x01;
-pub const JCMD_PAK_READ: u8 = 0x02;
-pub const JCMD_PAK_WRITE: u8 = 0x03;
-//pub const JCMD_VRU_READ: u8 = 0x09;
-//pub const JCMD_VRU_WRITE: u8 = 0x0A;
-//pub const JCMD_VRU_READ_STATUS: u8 = 0x0B;
-//pub const JCMD_VRU_WRITE_CONFIG: u8 = 0x0C;
-//pub const JCMD_VRU_WRITE_INIT: u8 = 0x0D;
-pub const JCMD_RESET: u8 = 0xff;
+const JCMD_STATUS: u8 = 0x00;
+const JCMD_CONTROLLER_READ: u8 = 0x01;
+const JCMD_PAK_READ: u8 = 0x02;
+const JCMD_PAK_WRITE: u8 = 0x03;
+//const JCMD_VRU_READ: u8 = 0x09;
+//const JCMD_VRU_WRITE: u8 = 0x0A;
+//const JCMD_VRU_READ_STATUS: u8 = 0x0B;
+//const JCMD_VRU_WRITE_CONFIG: u8 = 0x0C;
+//const JCMD_VRU_WRITE_INIT: u8 = 0x0D;
+const JCMD_RESET: u8 = 0xff;

-//pub const JDT_NONE: u16 = 0x0000;
-pub const JDT_JOY_ABS_COUNTERS: u16 = 0x0001; /* joystick with absolute coordinates */
-//pub const JDT_JOY_REL_COUNTERS: u16 = 0x0002; /* joystick with relative coordinates (= mouse) */
-pub const JDT_JOY_PORT: u16 = 0x0004; /* has port for external paks */
-//pub const JDT_VRU: u16 = 0x0100; /* VRU */
-pub const PAK_CHUNK_SIZE: usize = 0x20;
-pub const CONT_STATUS_PAK_NOT_PRESENT: u8 = 0;
-pub const CONT_STATUS_PAK_PRESENT: u8 = 1;
-pub const CONT_FLAVOR: u16 = JDT_JOY_ABS_COUNTERS | JDT_JOY_PORT;
+//const JDT_NONE: u16 = 0x0000;
+const JDT_JOY_ABS_COUNTERS: u16 = 0x0001; /* joystick with absolute coordinates */
+//const JDT_JOY_REL_COUNTERS: u16 = 0x0002; /* joystick with relative coordinates (= mouse) */
+const JDT_JOY_PORT: u16 = 0x0004; /* has port for external paks */
+//const JDT_VRU: u16 = 0x0100; /* VRU */
+const PAK_CHUNK_SIZE: usize = 0x20;
+const CONT_STATUS_PAK_NOT_PRESENT: u8 = 0;
+const CONT_STATUS_PAK_PRESENT: u8 = 1;
+const CONT_FLAVOR: u16 = JDT_JOY_ABS_COUNTERS | JDT_JOY_PORT;

 #[derive(Copy, Clone)]
 pub struct PakHandler {
--- a/src/device/cop0.rs
+++ b/src/device/cop0.rs
@ -1,37 +1,37 @@
 use crate::device;

 pub const COP0_INDEX_REG: u32 = 0;
-pub const COP0_RANDOM_REG: u32 = 1;
+const COP0_RANDOM_REG: u32 = 1;
 pub const COP0_ENTRYLO0_REG: u32 = 2;
 pub const COP0_ENTRYLO1_REG: u32 = 3;
 pub const COP0_CONTEXT_REG: u32 = 4;
 pub const COP0_PAGEMASK_REG: u32 = 5;
-pub const COP0_WIRED_REG: u32 = 6;
-//pub const COP0_UNUSED_7: u32 = 7;
+const COP0_WIRED_REG: u32 = 6;
+//const COP0_UNUSED_7: u32 = 7;
 pub const COP0_BADVADDR_REG: u32 = 8;
 pub const COP0_COUNT_REG: u32 = 9;
 pub const COP0_ENTRYHI_REG: u32 = 10;
-pub const COP0_COMPARE_REG: u32 = 11;
+const COP0_COMPARE_REG: u32 = 11;
 pub const COP0_STATUS_REG: u32 = 12;
 pub const COP0_CAUSE_REG: u32 = 13;
 pub const COP0_EPC_REG: u32 = 14;
-pub const COP0_PREVID_REG: u32 = 15;
-pub const COP0_CONFIG_REG: u32 = 16;
+const COP0_PREVID_REG: u32 = 15;
+const COP0_CONFIG_REG: u32 = 16;
 pub const COP0_LLADDR_REG: u32 = 17;
-//pub const COP0_WATCHLO_REG: u32 = 18;
-//pub const COP0_WATCHHI_REG: u32 = 19;
+//const COP0_WATCHLO_REG: u32 = 18;
+//const COP0_WATCHHI_REG: u32 = 19;
 pub const COP0_XCONTEXT_REG: u32 = 20;
-//pub const COP0_UNUSED_21: u32 = 21;
-//pub const COP0_UNUSED_22: u32 = 22;
-//pub const COP0_UNUSED_23: u32 = 23;
-//pub const COP0_UNUSED_24: u32 = 24;
-//pub const COP0_UNUSED_25: u32 = 25;
-//pub const COP0_PARITYERR_REG: u32 = 26;
-//pub const COP0_CACHEERR_REG: u32 = 27;
+//const COP0_UNUSED_21: u32 = 21;
+//const COP0_UNUSED_22: u32 = 22;
+//const COP0_UNUSED_23: u32 = 23;
+//const COP0_UNUSED_24: u32 = 24;
+//const COP0_UNUSED_25: u32 = 25;
+//const COP0_PARITYERR_REG: u32 = 26;
+//const COP0_CACHEERR_REG: u32 = 27;
 pub const COP0_TAGLO_REG: u32 = 28;
-//pub const COP0_TAGHI_REG: u32 = 29;
-pub const COP0_ERROREPC_REG: u32 = 30;
-//pub const COP0_UNUSED_31: u32 = 31;
+//const COP0_TAGHI_REG: u32 = 29;
+const COP0_ERROREPC_REG: u32 = 30;
+//const COP0_UNUSED_31: u32 = 31;
 pub const COP0_REGS_COUNT: u32 = 32;

 pub const COP0_STATUS_IE: u64 = 1 << 0;
@ -42,12 +42,12 @@ pub const COP0_STATUS_FR: u64 = 1 << 26;
 pub const COP0_STATUS_CU1: u64 = 1 << 29;
 pub const COP0_STATUS_CU2: u64 = 1 << 30;

-//pub const COP0_CAUSE_EXCCODE_INTR: u64 = 0 << 2;
+//const COP0_CAUSE_EXCCODE_INTR: u64 = 0 << 2;
 pub const COP0_CAUSE_EXCCODE_MOD: u64 = 1 << 2;
 pub const COP0_CAUSE_EXCCODE_TLBL: u64 = 2 << 2;
 pub const COP0_CAUSE_EXCCODE_TLBS: u64 = 3 << 2;
-//pub const COP0_CAUSE_EXCCODE_ADEL: u64 = 4 << 2;
-//pub const COP0_CAUSE_EXCCODE_ADES: u64 = 5 << 2;
+//const COP0_CAUSE_EXCCODE_ADEL: u64 = 4 << 2;
+//const COP0_CAUSE_EXCCODE_ADES: u64 = 5 << 2;
 pub const COP0_CAUSE_EXCCODE_SYS: u64 = 8 << 2;
 pub const COP0_CAUSE_EXCCODE_BP: u64 = 9 << 2;
 pub const COP0_CAUSE_EXCCODE_RI: u64 = 10 << 2;
@ -55,7 +55,7 @@ pub const COP0_CAUSE_EXCCODE_CPU: u64 = 11 << 2;
 pub const COP0_CAUSE_EXCCODE_TR: u64 = 13 << 2;
 pub const COP0_CAUSE_EXCCODE_FPE: u64 = 15 << 2;
 pub const COP0_CAUSE_IP2: u64 = 1 << 10;
-pub const COP0_CAUSE_IP7: u64 = 1 << 15;
+const COP0_CAUSE_IP7: u64 = 1 << 15;
 pub const COP0_CAUSE_BD: u64 = 1 << 31;

 pub const COP0_CAUSE_CE1: u64 = 1 << 28;
--- a/src/device/cop1.rs
+++ b/src/device/cop1.rs
@ -1,27 +1,27 @@
 use crate::device;

-//pub const FCR31_FLAG_INEXACT_BIT: u32 = 1 << 2;
-//pub const FCR31_FLAG_UNDERFLOW_BIT: u32 = 1 << 3;
-//pub const FCR31_FLAG_OVERFLOW_BIT: u32 = 1 << 4;
-//pub const FCR31_FLAG_DIVBYZERO_BIT: u32 = 1 << 5;
-//pub const FCR31_FLAG_INVALID_BIT: u32 = 1 << 6;
-//pub const FCR31_ENABLE_INEXACT_BIT: u32 = 1 << 7;
-//pub const FCR31_ENABLE_UNDERFLOW_BIT: u32 = 1 << 8;
-//pub const FCR31_ENABLE_OVERFLOW_BIT: u32 = 1 << 9;
-//pub const FCR31_ENABLE_DIVBYZERO_BIT: u32 = 1 << 10;
-//pub const FCR31_ENABLE_INVALID_BIT: u32 = 1 << 11;
-//pub const FCR31_CAUSE_INEXACT_BIT: u32 = 1 << 12;
-//pub const FCR31_CAUSE_UNDERFLOW_BIT: u32 = 1 << 13;
-//pub const FCR31_CAUSE_OVERFLOW_BIT: u32 = 1 << 14;
-//pub const FCR31_CAUSE_DIVBYZERO_BIT: u32 = 1 << 15;
-//pub const FCR31_CAUSE_INVALID_BIT: u32 = 1 << 16;
-pub const FCR31_CAUSE_UNIMP_BIT: u32 = 1 << 17;
+//const FCR31_FLAG_INEXACT_BIT: u32 = 1 << 2;
+//const FCR31_FLAG_UNDERFLOW_BIT: u32 = 1 << 3;
+//const FCR31_FLAG_OVERFLOW_BIT: u32 = 1 << 4;
+//const FCR31_FLAG_DIVBYZERO_BIT: u32 = 1 << 5;
+//const FCR31_FLAG_INVALID_BIT: u32 = 1 << 6;
+//const FCR31_ENABLE_INEXACT_BIT: u32 = 1 << 7;
+//const FCR31_ENABLE_UNDERFLOW_BIT: u32 = 1 << 8;
+//const FCR31_ENABLE_OVERFLOW_BIT: u32 = 1 << 9;
+//const FCR31_ENABLE_DIVBYZERO_BIT: u32 = 1 << 10;
+//const FCR31_ENABLE_INVALID_BIT: u32 = 1 << 11;
+//const FCR31_CAUSE_INEXACT_BIT: u32 = 1 << 12;
+//const FCR31_CAUSE_UNDERFLOW_BIT: u32 = 1 << 13;
+//const FCR31_CAUSE_OVERFLOW_BIT: u32 = 1 << 14;
+//const FCR31_CAUSE_DIVBYZERO_BIT: u32 = 1 << 15;
+//const FCR31_CAUSE_INVALID_BIT: u32 = 1 << 16;
+const FCR31_CAUSE_UNIMP_BIT: u32 = 1 << 17;
 pub const FCR31_CMP_BIT: u32 = 1 << 23;
-pub const FCR31_FS_BIT: u32 = 1 << 24;
+const FCR31_FS_BIT: u32 = 1 << 24;

-pub const FCR31_CAUSE_MASK: u32 = 0b00000000000000111111000000000000;
-pub const FCR31_ENABLE_MASK: u32 = 0b00000000000000000000111110000000;
-pub const FCR31_WRITE_MASK: u32 = 0b00000001100000111111111111111111;
+const FCR31_CAUSE_MASK: u32 = 0b00000000000000111111000000000000;
+const FCR31_ENABLE_MASK: u32 = 0b00000000000000000000111110000000;
+const FCR31_WRITE_MASK: u32 = 0b00000001100000111111111111111111;

 pub struct Cop1 {
    pub fcr0: u32,
--- a/src/device/is_viewer.rs
+++ b/src/device/is_viewer.rs
@ -1,6 +1,6 @@
 use crate::device;

-pub const IS_VIEWER_MASK: usize = 0xFFFF;
+const IS_VIEWER_MASK: usize = 0xFFFF;

 pub fn read_mem(
    device: &mut device::Device,
--- a/src/device/memory.rs
+++ b/src/device/memory.rs
@ -1,24 +1,24 @@
 use crate::device;

-pub const MM_RDRAM_DRAM: usize = 0x00000000;
-pub const MM_RDRAM_REGS: usize = 0x03f00000;
-pub const MM_RSP_MEM: usize = 0x04000000;
-pub const MM_RSP_REGS: usize = 0x04040000;
-pub const MM_RSP_REGS_PC: usize = 0x04080000;
-pub const MM_DPC_REGS: usize = 0x04100000;
-pub const MM_DPS_REGS: usize = 0x04200000;
-pub const MM_MI_REGS: usize = 0x04300000;
-pub const MM_VI_REGS: usize = 0x04400000;
-pub const MM_AI_REGS: usize = 0x04500000;
-pub const MM_PI_REGS: usize = 0x04600000;
-pub const MM_RI_REGS: usize = 0x04700000;
-pub const MM_SI_REGS: usize = 0x04800000;
+const MM_RDRAM_DRAM: usize = 0x00000000;
+const MM_RDRAM_REGS: usize = 0x03f00000;
+const MM_RSP_MEM: usize = 0x04000000;
+const MM_RSP_REGS: usize = 0x04040000;
+const MM_RSP_REGS_PC: usize = 0x04080000;
+const MM_DPC_REGS: usize = 0x04100000;
+const MM_DPS_REGS: usize = 0x04200000;
+const MM_MI_REGS: usize = 0x04300000;
+const MM_VI_REGS: usize = 0x04400000;
+const MM_AI_REGS: usize = 0x04500000;
+const MM_PI_REGS: usize = 0x04600000;
+const MM_RI_REGS: usize = 0x04700000;
+const MM_SI_REGS: usize = 0x04800000;
 //const MM_DOM2_ADDR1: usize = 0x05000000;
 pub const MM_DOM2_ADDR2: usize = 0x08000000;
 pub const MM_CART_ROM: usize = 0x10000000;
-pub const MM_PIF_MEM: usize = 0x1fc00000;
-//pub const MM_DOM1_ADDR3: usize = 0x1fd00000;
-pub const MM_IS_VIEWER: usize = 0x13ff0000;
+const MM_PIF_MEM: usize = 0x1fc00000;
+//const MM_DOM1_ADDR3: usize = 0x1fd00000;
+const MM_IS_VIEWER: usize = 0x13ff0000;

 #[derive(PartialEq)]
 pub enum AccessType {
--- a/src/device/mempak.rs
+++ b/src/device/mempak.rs
@ -1,7 +1,7 @@
 use crate::device;

-pub const MEMPAK_SIZE: usize = 0x8000;
-pub const MPK_PAGE_SIZE: usize = 256;
+const MEMPAK_SIZE: usize = 0x8000;
+const MPK_PAGE_SIZE: usize = 256;

 pub fn format_mempak(device: &mut device::Device) {
    if device.ui.saves.mempak.0.len() < MEMPAK_SIZE * 4 {
--- a/src/device/mi.rs
+++ b/src/device/mi.rs
@ -1,9 +1,9 @@
 use crate::device;

-pub const MI_INIT_MODE_REG: u32 = 0;
-pub const MI_VERSION_REG: u32 = 1;
-pub const MI_INTR_REG: u32 = 2;
-pub const MI_INTR_MASK_REG: u32 = 3;
+const MI_INIT_MODE_REG: u32 = 0;
+const MI_VERSION_REG: u32 = 1;
+const MI_INTR_REG: u32 = 2;
+const MI_INTR_MASK_REG: u32 = 3;
 pub const MI_REGS_COUNT: u32 = 4;

 /* read */
@ -15,34 +15,34 @@ pub const MI_INTR_PI: u32 = 1 << 4;
 pub const MI_INTR_DP: u32 = 1 << 5;

 /* write */
-pub const MI_CLR_SP: u32 = 1 << 0;
-pub const MI_SET_SP: u32 = 1 << 1;
-pub const MI_CLR_SI: u32 = 1 << 2;
-pub const MI_SET_SI: u32 = 1 << 3;
-pub const MI_CLR_AI: u32 = 1 << 4;
-pub const MI_SET_AI: u32 = 1 << 5;
-pub const MI_CLR_VI: u32 = 1 << 6;
-pub const MI_SET_VI: u32 = 1 << 7;
-pub const MI_CLR_PI: u32 = 1 << 8;
-pub const MI_SET_PI: u32 = 1 << 9;
-pub const MI_CLR_DP: u32 = 1 << 10;
-pub const MI_SET_DP: u32 = 1 << 11;
+const MI_CLR_SP: u32 = 1 << 0;
+const MI_SET_SP: u32 = 1 << 1;
+const MI_CLR_SI: u32 = 1 << 2;
+const MI_SET_SI: u32 = 1 << 3;
+const MI_CLR_AI: u32 = 1 << 4;
+const MI_SET_AI: u32 = 1 << 5;
+const MI_CLR_VI: u32 = 1 << 6;
+const MI_SET_VI: u32 = 1 << 7;
+const MI_CLR_PI: u32 = 1 << 8;
+const MI_SET_PI: u32 = 1 << 9;
+const MI_CLR_DP: u32 = 1 << 10;
+const MI_SET_DP: u32 = 1 << 11;

 /* mode read */
-pub const MI_INIT_MODE: u32 = 1 << 7;
-pub const MI_EBUS_MODE: u32 = 1 << 8;
-pub const MI_RDRAM_MODE: u32 = 1 << 9;
+const MI_INIT_MODE: u32 = 1 << 7;
+const MI_EBUS_MODE: u32 = 1 << 8;
+const MI_RDRAM_MODE: u32 = 1 << 9;

 /* mode write */
-pub const MI_CLR_INIT: u32 = 1 << 7;
-pub const MI_SET_INIT: u32 = 1 << 8;
-pub const MI_CLR_EBUS: u32 = 1 << 9;
-pub const MI_SET_EBUS: u32 = 1 << 10;
-pub const MI_CLR_DP_INTR: u32 = 1 << 11;
-pub const MI_CLR_RDRAM: u32 = 1 << 12;
-pub const MI_SET_RDRAM: u32 = 1 << 13;
+const MI_CLR_INIT: u32 = 1 << 7;
+const MI_SET_INIT: u32 = 1 << 8;
+const MI_CLR_EBUS: u32 = 1 << 9;
+const MI_SET_EBUS: u32 = 1 << 10;
+const MI_CLR_DP_INTR: u32 = 1 << 11;
+const MI_CLR_RDRAM: u32 = 1 << 12;
+const MI_SET_RDRAM: u32 = 1 << 13;

-pub const MI_INIT_LENGTH_MASK: u32 = 0b1111111;
+const MI_INIT_LENGTH_MASK: u32 = 0b1111111;

 pub struct Mi {
    pub regs: [u32; MI_REGS_COUNT as usize],
--- a/src/device/pi.rs
+++ b/src/device/pi.rs
@ -1,29 +1,29 @@
 use crate::device;

-pub const PI_DRAM_ADDR_REG: u32 = 0;
-pub const PI_CART_ADDR_REG: u32 = 1;
-pub const PI_RD_LEN_REG: u32 = 2;
-pub const PI_WR_LEN_REG: u32 = 3;
+const PI_DRAM_ADDR_REG: u32 = 0;
+const PI_CART_ADDR_REG: u32 = 1;
+const PI_RD_LEN_REG: u32 = 2;
+const PI_WR_LEN_REG: u32 = 3;
 pub const PI_STATUS_REG: u32 = 4;
-pub const PI_BSD_DOM1_LAT_REG: u32 = 5;
-pub const PI_BSD_DOM1_PWD_REG: u32 = 6;
-pub const PI_BSD_DOM1_PGS_REG: u32 = 7;
-pub const PI_BSD_DOM1_RLS_REG: u32 = 8;
-pub const PI_BSD_DOM2_LAT_REG: u32 = 9;
-pub const PI_BSD_DOM2_PWD_REG: u32 = 10;
-pub const PI_BSD_DOM2_PGS_REG: u32 = 11;
-pub const PI_BSD_DOM2_RLS_REG: u32 = 12;
+const PI_BSD_DOM1_LAT_REG: u32 = 5;
+const PI_BSD_DOM1_PWD_REG: u32 = 6;
+const PI_BSD_DOM1_PGS_REG: u32 = 7;
+const PI_BSD_DOM1_RLS_REG: u32 = 8;
+const PI_BSD_DOM2_LAT_REG: u32 = 9;
+const PI_BSD_DOM2_PWD_REG: u32 = 10;
+const PI_BSD_DOM2_PGS_REG: u32 = 11;
+const PI_BSD_DOM2_RLS_REG: u32 = 12;
 pub const PI_REGS_COUNT: u32 = 13;

 /* PI_STATUS - read */
-pub const PI_STATUS_DMA_BUSY: u32 = 1 << 0;
+const PI_STATUS_DMA_BUSY: u32 = 1 << 0;
 pub const PI_STATUS_IO_BUSY: u32 = 1 << 1;
-//pub const PI_STATUS_ERROR: u32 = 1 << 2;
-pub const PI_STATUS_INTERRUPT: u32 = 1 << 3;
+//const PI_STATUS_ERROR: u32 = 1 << 2;
+const PI_STATUS_INTERRUPT: u32 = 1 << 3;

 /* PI_STATUS - write */
-pub const PI_STATUS_RESET: u32 = 1 << 0;
-pub const PI_STATUS_CLR_INTR: u32 = 1 << 1;
+const PI_STATUS_RESET: u32 = 1 << 0;
+const PI_STATUS_CLR_INTR: u32 = 1 << 1;

 pub struct Pi {
    pub regs: [u32; PI_REGS_COUNT as usize],
--- a/src/device/rdp.rs
+++ b/src/device/rdp.rs
@ -5,41 +5,41 @@ pub const DPC_START_REG: u32 = 0;
 pub const DPC_END_REG: u32 = 1;
 pub const DPC_CURRENT_REG: u32 = 2;
 pub const DPC_STATUS_REG: u32 = 3;
-pub const DPC_CLOCK_REG: u32 = 4;
-pub const DPC_BUFBUSY_REG: u32 = 5;
-pub const DPC_PIPEBUSY_REG: u32 = 6;
-pub const DPC_TMEM_REG: u32 = 7;
+const DPC_CLOCK_REG: u32 = 4;
+const DPC_BUFBUSY_REG: u32 = 5;
+const DPC_PIPEBUSY_REG: u32 = 6;
+const DPC_TMEM_REG: u32 = 7;
 pub const DPC_REGS_COUNT: u32 = 8;

-//pub const DPS_TBIST_REG: u32 = 0;
-//pub const DPS_TEST_MODE_REG: u32 = 1;
-//pub const DPS_BUFTEST_ADDR_REG: u32 = 2;
-//pub const DPS_BUFTEST_DATA_REG: u32 = 3;
+//const DPS_TBIST_REG: u32 = 0;
+//const DPS_TEST_MODE_REG: u32 = 1;
+//const DPS_BUFTEST_ADDR_REG: u32 = 2;
+//const DPS_BUFTEST_DATA_REG: u32 = 3;
 pub const DPS_REGS_COUNT: u32 = 4;

 /* DPC status - read */
-pub const DPC_STATUS_XBUS_DMEM_DMA: u32 = 1 << 0;
-pub const DPC_STATUS_FREEZE: u32 = 1 << 1;
-pub const DPC_STATUS_FLUSH: u32 = 1 << 2;
-pub const DPC_STATUS_START_GCLK: u32 = 1 << 3;
-pub const DPC_STATUS_TMEM_BUSY: u32 = 1 << 4;
-pub const DPC_STATUS_PIPE_BUSY: u32 = 1 << 5;
-pub const DPC_STATUS_CMD_BUSY: u32 = 1 << 6;
-pub const DPC_STATUS_CBUF_READY: u32 = 1 << 7;
-//pub const DPC_STATUS_DMA_BUSY: u32 = 1 << 8;
-//pub const DPC_STATUS_END_VALID: u32 = 1 << 9;
-pub const DPC_STATUS_START_VALID: u32 = 1 << 10;
+const DPC_STATUS_XBUS_DMEM_DMA: u32 = 1 << 0;
+const DPC_STATUS_FREEZE: u32 = 1 << 1;
+const DPC_STATUS_FLUSH: u32 = 1 << 2;
+const DPC_STATUS_START_GCLK: u32 = 1 << 3;
+const DPC_STATUS_TMEM_BUSY: u32 = 1 << 4;
+const DPC_STATUS_PIPE_BUSY: u32 = 1 << 5;
+const DPC_STATUS_CMD_BUSY: u32 = 1 << 6;
+const DPC_STATUS_CBUF_READY: u32 = 1 << 7;
+//const DPC_STATUS_DMA_BUSY: u32 = 1 << 8;
+//const DPC_STATUS_END_VALID: u32 = 1 << 9;
+const DPC_STATUS_START_VALID: u32 = 1 << 10;
 /* DPC status - write */
-pub const DPC_CLR_XBUS_DMEM_DMA: u32 = 1 << 0;
-pub const DPC_SET_XBUS_DMEM_DMA: u32 = 1 << 1;
-pub const DPC_CLR_FREEZE: u32 = 1 << 2;
-pub const DPC_SET_FREEZE: u32 = 1 << 3;
-pub const DPC_CLR_FLUSH: u32 = 1 << 4;
-pub const DPC_SET_FLUSH: u32 = 1 << 5;
-pub const DPC_CLR_TMEM_CTR: u32 = 1 << 6;
-pub const DPC_CLR_PIPE_CTR: u32 = 1 << 7;
-pub const DPC_CLR_CMD_CTR: u32 = 1 << 8;
-pub const DPC_CLR_CLOCK_CTR: u32 = 1 << 9;
+const DPC_CLR_XBUS_DMEM_DMA: u32 = 1 << 0;
+const DPC_SET_XBUS_DMEM_DMA: u32 = 1 << 1;
+const DPC_CLR_FREEZE: u32 = 1 << 2;
+const DPC_SET_FREEZE: u32 = 1 << 3;
+const DPC_CLR_FLUSH: u32 = 1 << 4;
+const DPC_SET_FLUSH: u32 = 1 << 5;
+const DPC_CLR_TMEM_CTR: u32 = 1 << 6;
+const DPC_CLR_PIPE_CTR: u32 = 1 << 7;
+const DPC_CLR_CMD_CTR: u32 = 1 << 8;
+const DPC_CLR_CLOCK_CTR: u32 = 1 << 9;

 pub struct Rdp {
    pub regs_dpc: [u32; DPC_REGS_COUNT as usize],
--- a/src/device/ri.rs
+++ b/src/device/ri.rs
@ -1,13 +1,13 @@
 use crate::device;

-//pub const RI_MODE_REG: u32 = 0;
-//pub const RI_CONFIG_REG: u32 = 1;
-//pub const RI_CURRENT_LOAD_REG: u32 = 2;
-pub const RI_SELECT_REG: u32 = 3;
-//pub const RI_REFRESH_REG: u32 = 4;
-//pub const RI_LATENCY_REG: u32 = 5;
-//pub const RI_ERROR_REG: u32 = 6;
-//pub const RI_WERROR_REG: u32 = 7;
+//const RI_MODE_REG: u32 = 0;
+//const RI_CONFIG_REG: u32 = 1;
+//const RI_CURRENT_LOAD_REG: u32 = 2;
+const RI_SELECT_REG: u32 = 3;
+//const RI_REFRESH_REG: u32 = 4;
+//const RI_LATENCY_REG: u32 = 5;
+//const RI_ERROR_REG: u32 = 6;
+//const RI_WERROR_REG: u32 = 7;
 pub const RI_REGS_COUNT: u32 = 8;

 pub struct Ri {
--- a/src/device/rsp_interface.rs
+++ b/src/device/rsp_interface.rs
@ -1,64 +1,64 @@
 use crate::device;

-pub const SP_MEM_ADDR_REG: u32 = 0;
-pub const SP_DRAM_ADDR_REG: u32 = 1;
-pub const SP_RD_LEN_REG: u32 = 2;
-pub const SP_WR_LEN_REG: u32 = 3;
+const SP_MEM_ADDR_REG: u32 = 0;
+const SP_DRAM_ADDR_REG: u32 = 1;
+const SP_RD_LEN_REG: u32 = 2;
+const SP_WR_LEN_REG: u32 = 3;
 pub const SP_STATUS_REG: u32 = 4;
-pub const SP_DMA_FULL_REG: u32 = 5;
-pub const SP_DMA_BUSY_REG: u32 = 6;
-pub const SP_SEMAPHORE_REG: u32 = 7;
+const SP_DMA_FULL_REG: u32 = 5;
+const SP_DMA_BUSY_REG: u32 = 6;
+const SP_SEMAPHORE_REG: u32 = 7;
 pub const SP_REGS_COUNT: u32 = 8;

 pub const SP_PC_REG: u32 = 0;
-//pub const SP_IBIST_REG: u32 = 1;
+//const SP_IBIST_REG: u32 = 1;
 pub const SP_REGS2_COUNT: u32 = 2;

 /* SP_STATUS - read */
 pub const SP_STATUS_HALT: u32 = 1 << 0;
-pub const SP_STATUS_BROKE: u32 = 1 << 1;
-pub const SP_STATUS_DMA_BUSY: u32 = 1 << 2;
-pub const SP_STATUS_DMA_FULL: u32 = 1 << 3;
-//pub const SP_STATUS_IO_FULL: u32 = 1 << 4;
-pub const SP_STATUS_SSTEP: u32 = 1 << 5;
-pub const SP_STATUS_INTR_BREAK: u32 = 1 << 6;
-pub const SP_STATUS_SIG0: u32 = 1 << 7;
-pub const SP_STATUS_SIG1: u32 = 1 << 8;
-pub const SP_STATUS_SIG2: u32 = 1 << 9;
-pub const SP_STATUS_SIG3: u32 = 1 << 10;
-pub const SP_STATUS_SIG4: u32 = 1 << 11;
-pub const SP_STATUS_SIG5: u32 = 1 << 12;
-pub const SP_STATUS_SIG6: u32 = 1 << 13;
-pub const SP_STATUS_SIG7: u32 = 1 << 14;
+const SP_STATUS_BROKE: u32 = 1 << 1;
+const SP_STATUS_DMA_BUSY: u32 = 1 << 2;
+const SP_STATUS_DMA_FULL: u32 = 1 << 3;
+//const SP_STATUS_IO_FULL: u32 = 1 << 4;
+const SP_STATUS_SSTEP: u32 = 1 << 5;
+const SP_STATUS_INTR_BREAK: u32 = 1 << 6;
+const SP_STATUS_SIG0: u32 = 1 << 7;
+const SP_STATUS_SIG1: u32 = 1 << 8;
+const SP_STATUS_SIG2: u32 = 1 << 9;
+const SP_STATUS_SIG3: u32 = 1 << 10;
+const SP_STATUS_SIG4: u32 = 1 << 11;
+const SP_STATUS_SIG5: u32 = 1 << 12;
+const SP_STATUS_SIG6: u32 = 1 << 13;
+const SP_STATUS_SIG7: u32 = 1 << 14;

 /* SP_STATUS - write */
-pub const SP_CLR_HALT: u32 = 1 << 0;
+const SP_CLR_HALT: u32 = 1 << 0;
 pub const SP_SET_HALT: u32 = 1 << 1;
-pub const SP_CLR_BROKE: u32 = 1 << 2;
-pub const SP_CLR_INTR: u32 = 1 << 3;
-pub const SP_SET_INTR: u32 = 1 << 4;
-pub const SP_CLR_SSTEP: u32 = 1 << 5;
-pub const SP_SET_SSTEP: u32 = 1 << 6;
-pub const SP_CLR_INTR_BREAK: u32 = 1 << 7;
-pub const SP_SET_INTR_BREAK: u32 = 1 << 8;
-pub const SP_CLR_SIG0: u32 = 1 << 9;
-pub const SP_SET_SIG0: u32 = 1 << 10;
-pub const SP_CLR_SIG1: u32 = 1 << 11;
-pub const SP_SET_SIG1: u32 = 1 << 12;
-pub const SP_CLR_SIG2: u32 = 1 << 13;
-pub const SP_SET_SIG2: u32 = 1 << 14;
-pub const SP_CLR_SIG3: u32 = 1 << 15;
-pub const SP_SET_SIG3: u32 = 1 << 16;
-pub const SP_CLR_SIG4: u32 = 1 << 17;
-pub const SP_SET_SIG4: u32 = 1 << 18;
-pub const SP_CLR_SIG5: u32 = 1 << 19;
-pub const SP_SET_SIG5: u32 = 1 << 20;
-pub const SP_CLR_SIG6: u32 = 1 << 21;
-pub const SP_SET_SIG6: u32 = 1 << 22;
-pub const SP_CLR_SIG7: u32 = 1 << 23;
-pub const SP_SET_SIG7: u32 = 1 << 24;
+const SP_CLR_BROKE: u32 = 1 << 2;
+const SP_CLR_INTR: u32 = 1 << 3;
+const SP_SET_INTR: u32 = 1 << 4;
+const SP_CLR_SSTEP: u32 = 1 << 5;
+const SP_SET_SSTEP: u32 = 1 << 6;
+const SP_CLR_INTR_BREAK: u32 = 1 << 7;
+const SP_SET_INTR_BREAK: u32 = 1 << 8;
+const SP_CLR_SIG0: u32 = 1 << 9;
+const SP_SET_SIG0: u32 = 1 << 10;
+const SP_CLR_SIG1: u32 = 1 << 11;
+const SP_SET_SIG1: u32 = 1 << 12;
+const SP_CLR_SIG2: u32 = 1 << 13;
+const SP_SET_SIG2: u32 = 1 << 14;
+const SP_CLR_SIG3: u32 = 1 << 15;
+const SP_SET_SIG3: u32 = 1 << 16;
+const SP_CLR_SIG4: u32 = 1 << 17;
+const SP_SET_SIG4: u32 = 1 << 18;
+const SP_CLR_SIG5: u32 = 1 << 19;
+const SP_SET_SIG5: u32 = 1 << 20;
+const SP_CLR_SIG6: u32 = 1 << 21;
+const SP_SET_SIG6: u32 = 1 << 22;
+const SP_CLR_SIG7: u32 = 1 << 23;
+const SP_SET_SIG7: u32 = 1 << 24;

-pub const RSP_MEM_MASK: usize = 0x1FFF;
+const RSP_MEM_MASK: usize = 0x1FFF;

 #[derive(PartialEq, Copy, Clone)]
 pub enum DmaDir {
--- a/src/device/si.rs
+++ b/src/device/si.rs
@ -1,18 +1,18 @@
 use crate::device;

-pub const SI_DRAM_ADDR_REG: u32 = 0;
-pub const SI_PIF_ADDR_RD64B_REG: u32 = 1;
-//pub const SI_R2_REG: u32 = 2;
-//pub const SI_R3_REG: u32 = 3;
-pub const SI_PIF_ADDR_WR64B_REG: u32 = 4;
-//pub const SI_R5_REG: u32 = 5;
+const SI_DRAM_ADDR_REG: u32 = 0;
+const SI_PIF_ADDR_RD64B_REG: u32 = 1;
+//const SI_R2_REG: u32 = 2;
+//const SI_R3_REG: u32 = 3;
+const SI_PIF_ADDR_WR64B_REG: u32 = 4;
+//const SI_R5_REG: u32 = 5;
 pub const SI_STATUS_REG: u32 = 6;
 pub const SI_REGS_COUNT: u32 = 7;

 pub const SI_STATUS_DMA_BUSY: u32 = 1 << 0;
 pub const SI_STATUS_IO_BUSY: u32 = 1 << 1;
-//pub const SI_STATUS_DMA_ERROR: u32 = 1 << 3;
-pub const SI_STATUS_INTERRUPT: u32 = 1 << 12;
+//const SI_STATUS_DMA_ERROR: u32 = 1 << 3;
+const SI_STATUS_INTERRUPT: u32 = 1 << 12;

 #[derive(PartialEq)]
 pub enum DmaDir {
--- a/src/device/sram.rs
+++ b/src/device/sram.rs
@ -1,13 +1,13 @@
 use crate::device;
 use crate::ui;

-pub const SRAM_MASK: usize = 0xFFFF;
-pub const SRAM_SIZE: usize = 0x8000;
-pub const FLASHRAM_SIZE: usize = 0x20000;
+const SRAM_MASK: usize = 0xFFFF;
+const SRAM_SIZE: usize = 0x8000;
+const FLASHRAM_SIZE: usize = 0x20000;
 pub const FLASHRAM_TYPE_ID: u32 = 0x11118001;
 pub const MX29L1100_ID: u32 = 0x00c2001e;
-pub const MX29L0000_ID: u32 = 0x00c20000;
-pub const MX29L0001_ID: u32 = 0x00c20001;
+const MX29L0000_ID: u32 = 0x00c20000;
+const MX29L0001_ID: u32 = 0x00c20001;

 #[derive(PartialEq)]
 pub enum FlashramMode {
--- a/src/device/vi.rs
+++ b/src/device/vi.rs
@ -2,18 +2,18 @@ use crate::device;
 use crate::ui;
 use governor::clock::Clock;

-pub const VI_STATUS_REG: u32 = 0;
-//pub const VI_ORIGIN_REG: u32 = 1;
+const VI_STATUS_REG: u32 = 0;
+//const VI_ORIGIN_REG: u32 = 1;
 pub const VI_WIDTH_REG: u32 = 2;
-//pub const VI_V_INTR_REG: u32 = 3;
-pub const VI_CURRENT_REG: u32 = 4;
-//pub const VI_BURST_REG: u32 = 5;
-pub const VI_V_SYNC_REG: u32 = 6;
-pub const VI_H_SYNC_REG: u32 = 7;
-//pub const VI_LEAP_REG: u32 = 8;
+//const VI_V_INTR_REG: u32 = 3;
+const VI_CURRENT_REG: u32 = 4;
+//const VI_BURST_REG: u32 = 5;
+const VI_V_SYNC_REG: u32 = 6;
+const VI_H_SYNC_REG: u32 = 7;
+//const VI_LEAP_REG: u32 = 8;
 pub const VI_H_START_REG: u32 = 9;
 pub const VI_V_START_REG: u32 = 10;
-//pub const VI_V_BURST_REG: u32 = 11;
+//const VI_V_BURST_REG: u32 = 11;
 pub const VI_X_SCALE_REG: u32 = 12;
 pub const VI_Y_SCALE_REG: u32 = 13;
 pub const VI_REGS_COUNT: u32 = 14;
--- a/src/ui/input.rs
+++ b/src/ui/input.rs
@ -2,29 +2,29 @@ use std::ops::Neg;

 use crate::ui;

-pub const R_DPAD: usize = 0;
-pub const L_DPAD: usize = 1;
-pub const D_DPAD: usize = 2;
-pub const U_DPAD: usize = 3;
-pub const START_BUTTON: usize = 4;
-pub const Z_TRIG: usize = 5;
-pub const B_BUTTON: usize = 6;
-pub const A_BUTTON: usize = 7;
-pub const R_CBUTTON: usize = 8;
-pub const L_CBUTTON: usize = 9;
-pub const D_CBUTTON: usize = 10;
-pub const U_CBUTTON: usize = 11;
-pub const R_TRIG: usize = 12;
-pub const L_TRIG: usize = 13;
-pub const X_AXIS: usize = 16;
-pub const Y_AXIS: usize = 24;
+const R_DPAD: usize = 0;
+const L_DPAD: usize = 1;
+const D_DPAD: usize = 2;
+const U_DPAD: usize = 3;
+const START_BUTTON: usize = 4;
+const Z_TRIG: usize = 5;
+const B_BUTTON: usize = 6;
+const A_BUTTON: usize = 7;
+const R_CBUTTON: usize = 8;
+const L_CBUTTON: usize = 9;
+const D_CBUTTON: usize = 10;
+const U_CBUTTON: usize = 11;
+const R_TRIG: usize = 12;
+const L_TRIG: usize = 13;
+const X_AXIS: usize = 16;
+const Y_AXIS: usize = 24;

-pub const AXIS_LEFT: usize = 14;
-pub const AXIS_RIGHT: usize = 15;
-pub const AXIS_UP: usize = 16;
-pub const AXIS_DOWN: usize = 17;
+const AXIS_LEFT: usize = 14;
+const AXIS_RIGHT: usize = 15;
+const AXIS_UP: usize = 16;
+const AXIS_DOWN: usize = 17;

-pub const MAX_AXIS_VALUE: f64 = 85.0;
+const MAX_AXIS_VALUE: f64 = 85.0;

 pub struct Controllers {
    pub game_controller: Option<sdl2::controller::GameController>,