203 lines
6.3 KiB
Rust
203 lines
6.3 KiB
Rust
use crate::device;
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use sha2::{Digest, Sha256};
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pub enum CicType {
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CicNus6101,
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CicNus6102,
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CicNus6103,
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CicNus6105,
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CicNus6106,
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CicNus5167,
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}
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const CART_MASK: usize = 0xFFFFFFF;
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pub struct Cart {
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pub rom: Vec<u8>,
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pub is_viewer_buffer: [u8; 0xFFFF],
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pub pal: bool,
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pub latch: u32,
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pub cic_type: CicType,
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pub cic_seed: u8,
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pub rdram_size_offset: usize,
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pub rtc: device::cart::AfRtc,
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}
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pub fn read_mem_fast(
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device: &mut device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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let masked_address = address as usize & CART_MASK;
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u32::from_be_bytes(
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device.cart.rom[masked_address..masked_address + 4]
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.try_into()
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.unwrap(),
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)
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}
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pub fn read_mem(
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device: &mut device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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let cycles = device::pi::calculate_cycles(device, 1, 4);
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device::cop0::add_cycles(device, cycles);
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// well known cart ROM oddity, if a read is perfomed while PI_STATUS_IO_BUSY is set, the latched value is returned rather than the data at the specified address
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if device.pi.regs[device::pi::PI_STATUS_REG as usize] & device::pi::PI_STATUS_IO_BUSY != 0 {
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device.cart.latch
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} else {
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let masked_address = address as usize & CART_MASK;
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u32::from_be_bytes(
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device.cart.rom[masked_address..masked_address + 4]
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.try_into()
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.unwrap(),
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)
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}
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}
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pub fn write_mem(device: &mut device::Device, _address: u64, value: u32, mask: u32) {
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device.cart.latch = value & mask;
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device.pi.regs[device::pi::PI_STATUS_REG as usize] |= device::pi::PI_STATUS_IO_BUSY;
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let cycles = device::pi::calculate_cycles(device, 1, 4);
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device::events::create_event(
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device,
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device::events::EventType::PI,
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device.cpu.cop0.regs[device::cop0::COP0_COUNT_REG as usize] + cycles,
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device::pi::dma_event,
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);
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}
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pub fn dma_read(
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device: &mut device::Device,
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mut cart_addr: u32,
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mut dram_addr: u32,
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length: u32,
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) -> u64 {
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dram_addr &= device::rdram::RDRAM_MASK as u32;
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cart_addr &= CART_MASK as u32;
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for i in 0..length {
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if cart_addr + i < device.cart.rom.len() as u32 {
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device.cart.rom[(cart_addr + i) as usize] =
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device.rdram.mem[(dram_addr + i) as usize ^ device.byte_swap];
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device.ui.saves.romsave.0.insert(
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(cart_addr + i).to_string(),
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serde_json::to_value(device.rdram.mem[(dram_addr + i) as usize ^ device.byte_swap])
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.unwrap(),
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);
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}
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}
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device.ui.saves.romsave.1 = true;
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device::pi::calculate_cycles(device, 1, length)
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}
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// cart is big endian, rdram is native endian
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pub fn dma_write(
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device: &mut device::Device,
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mut cart_addr: u32,
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mut dram_addr: u32,
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length: u32,
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) -> u64 {
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dram_addr &= device::rdram::RDRAM_MASK as u32;
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cart_addr &= CART_MASK as u32;
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let mut i = dram_addr;
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let mut j = cart_addr;
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while i < dram_addr + length && j < device.cart.rom.len() as u32 {
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device.rdram.mem[i as usize ^ device.byte_swap] = device.cart.rom[j as usize];
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i += 1;
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j += 1;
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}
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while i < dram_addr + length {
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// DMAs that extend past the end of the ROM return 0's for the portion that extends past the ROM length
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device.rdram.mem[i as usize ^ device.byte_swap] = 0;
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i += 1;
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}
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device::pi::calculate_cycles(device, 1, length)
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}
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pub fn init(device: &mut device::Device, rom_file: Vec<u8>) {
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device.cart.rom = rom_file;
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set_system_region(device, device.cart.rom[0x3E]);
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set_cic(device);
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device.ui.game_hash = calculate_hash(&device.cart.rom);
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device.ui.game_id = String::from_utf8(device.cart.rom[0x3B..0x3E].to_vec()).unwrap();
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if device.ui.game_id.contains('\0') {
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device.ui.game_id = String::from("UNK");
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}
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}
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pub fn load_rom_save(device: &mut device::Device) {
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if device.ui.saves.romsave.0.is_empty() {
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return;
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}
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for (key, value) in device.ui.saves.romsave.0.iter() {
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device.cart.rom[key.parse::<usize>().unwrap()] =
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serde_json::from_value(value.clone()).unwrap()
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}
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}
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pub fn set_system_region(device: &mut device::Device, country: u8) {
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let pal_codes: [u8; 8] = [b'D', b'F', b'I', b'P', b'S', b'U', b'X', b'Y'];
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for i in pal_codes {
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if country == i {
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device.cart.pal = true
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}
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}
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}
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pub fn set_cic(device: &mut device::Device) {
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let hash = calculate_hash(&device.cart.rom[0x40..0x1000]);
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match hash.as_str() {
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"B99F06C4802C2377E31E388435955EF3E99C618A6D55D24699D828EB1075F1EB" => {
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device.cart.cic_type = CicType::CicNus6101;
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device.cart.cic_seed = 0x3F;
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device.cart.rdram_size_offset = 0x318;
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}
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"61E88238552C356C23D19409FE5570EE6910419586BC6FC740F638F761ADC46E" => {
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device.cart.cic_type = CicType::CicNus6102;
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device.cart.cic_seed = 0x3F;
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device.cart.rdram_size_offset = 0x318;
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}
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"BF3620D30817007091EBE9BDDD1B88C23B8A0052170B3309CDE5B6B4238E45E7" => {
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device.cart.cic_type = CicType::CicNus6103;
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device.cart.cic_seed = 0x78;
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device.cart.rdram_size_offset = 0x318;
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}
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"04B7BC6717A9F0EB724CF927E74AD3876C381CBB280D841736FC5E55580B756B" => {
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device.cart.cic_type = CicType::CicNus6105;
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device.cart.cic_seed = 0x91;
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device.cart.rdram_size_offset = 0x3F0;
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}
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"36ADC40148AF56F0D78CD505EB6A90117D1FD6F11C6309E52ED36BC4C6BA340E" => {
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device.cart.cic_type = CicType::CicNus6106;
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device.cart.cic_seed = 0x85;
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device.cart.rdram_size_offset = 0x318;
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}
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"53C0088FB777870D0AF32F0251E964030E2E8B72E830C26042FD191169508C05" => {
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device.cart.cic_type = CicType::CicNus5167;
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device.cart.cic_seed = 0xdd;
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device.cart.rdram_size_offset = 0x318;
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}
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_ => {
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device.cart.cic_type = CicType::CicNus6102;
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device.cart.cic_seed = 0x3F;
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device.cart.rdram_size_offset = 0x318;
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println!("unknown IPL3 {}", hash)
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}
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}
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}
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fn calculate_hash(data: &[u8]) -> String {
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let mut hasher = Sha256::new();
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hasher.update(data);
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format!("{:X}", hasher.finalize())
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}
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